Method and apparatus for conserving power by throttling instruction fetching when a processor encounters low confidence branches in an information handling system
US7627742B2 · kind B2 · utility
17Cited by
18References
17Claims
0Family size
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Key dates
| Filing date | Apr 10, 2007 |
| Grant date | Dec 1, 2009 |
| Priority date | — |
| Expiry date | Jan 8, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3806
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An information handling system includes a processor that throttles the instruction fetcher whenever the inaccuracy, or lack of confidence, in branch predictions for branch instructions stored in a branch instruction queue exceeds a predetermined threshold confidence level of inaccuracy or error. In this manner, fetch operations slow down to conserve processor power when it is likely that the processor will mispredict the outcome of branch instructions. Fetch operations return to full speed when it is likely that the processor will correctly predict the outcome of branch instructions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.