Apparatus and method for discrete test access control of multiple cores
US7627794B2 · kind B2 · utility
10Cited by
3References
5Claims
0Family size
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Key dates
| Filing date | May 25, 2006 |
| Grant date | Dec 1, 2009 |
| Priority date | — |
| Expiry date | Jun 23, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31723
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An electronic circuit includes multiple computational cores. A test access protocol machine with a core address register and a signal routing control circuit addresses a selected computational core as specified by the core address register and routes output test data from the selected computational core.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.