Methods of forming void-free layers in openings of semiconductor substrates
US7629217B2 · kind B2 · utility
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25Claims
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Key dates
| Filing date | Apr 15, 2005 |
| Grant date | Dec 8, 2009 |
| Priority date | — |
| Expiry date | Apr 18, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
Abstract
In a method of manufacturing a floating gate of a non-volatile semiconductor memory, a pattern is formed on a substrate to have an opening that exposes a portion of the substrate. A first preliminary polysilicon layer is formed on the pattern and the exposed portion of the substrate to substantially fill the opening. A first polysilicon layer is formed by partially etching the first preliminary polysilicon layer until a first void formed in the first preliminary polysilicon layer is exposed. A second polysilicon layer is formed on the first polysilicon layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.