Hybrid crystal orientation CMOS structure for adaptive well biasing and for power and performance enhancement
US7629233B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 24, 2007 |
| Grant date | Dec 8, 2009 |
| Priority date | — |
| Expiry date | Apr 24, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D87/00
Abstract
The present invention provides a semiconducting structure including a substrate having an SOI region and a bulk-Si region, wherein the SOI region and the bulk-Si region have a same or differing crystallographic orientation; an isolation region separating the SOI region from the bulk-Si region; and at least one first device located in the SOI region and at least one second device located in the bulk-Si region. The SOI region has an silicon layer atop an insulating layer. The bulk-Si region further comprises a well region underlying the second device and a contact to the well region, wherein the contact stabilizes floating body effects. The well contact is also used to control the threshold voltages of the FETs in the bulk-Si region to optimized the power and performance of circuits built from the combination of the SOI and bulk-Si region FETs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.