Method for fabricating a nitride FET including passivation layers
US7632726B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 7, 2007 |
| Grant date | Dec 15, 2009 |
| Priority date | — |
| Expiry date | Dec 7, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/8503
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a nitride-based FET device that provides reduced electron trapping and gate current leakage. The fabrication method provides a device that includes a relatively thick passivation layer to reduce traps caused by device processing and a thin passivation layer below the gate terminal to reduce gate current leakage. Semiconductor device layers are deposited on a substrate. A plurality of passivation layers are deposited on the semiconductor device layers, where at least two of the layers are made of a different dielectric material to provide an etch stop. One or more of the passivation layers can be removed using the interfaces between the layers as an etch stop so that the distance between the gate terminal and the semiconductor device layers can be tightly controlled, where the distance can be made very thin to increase device performance and reduce gate current leakage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.