On-die anti-resonance structure for integrated circuit
US7633773B2 · kind B2 · utility
5Cited by
8References
19Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 10, 2006 |
| Grant date | Dec 15, 2009 |
| Priority date | — |
| Expiry date | May 26, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A structure and method for reducing the effects of chip-package resonance in an integrated circuit assembly is described. A series RLC circuit is employed to reduce the output impedance of the power delivery system at the resonance frequency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.