ROM memory component featuring reduced leakage current, and method for writing the same
US7633787B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 18, 2005 |
| Grant date | Dec 15, 2009 |
| Priority date | — |
| Expiry date | Aug 18, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2227
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention relates to a ROM memory cell comprising a first terminal connected to a word line, comprising a second terminal and comprising a third terminal, the second terminal being connected to a bit line and/or the third terminal being connected to a supply line for precharging the third terminal. The ROM memory cell according to the invention is distinguished by the fact that the same reference potential is in each case applied to the first terminal, the second terminal and/or the third terminal in a standby operating mode. The invention furthermore relates to a ROM memory component comprising such ROM memory cells, and to a method for reading from the ROM memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.