Method for manufacturing a vertical transistor that includes a super junction structure
US7635622B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 9, 2007 |
| Grant date | Dec 22, 2009 |
| Priority date | — |
| Expiry date | Dec 29, 2027 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/977
Abstract
A manufacturing method of a semiconductor device includes: forming multiple trenches on a semiconductor substrate; forming a second conductive type semiconductor film in each trench to provide a first column with the substrate between two trenches and a second column with the second conductive type semiconductor film in the trench, the first and second columns alternately repeated along with a predetermined direction; thinning a second side of the substrate; and increasing an impurity concentration in a thinned second side so that a first conductive type layer is provided. The impurity concentration of the first conductive type layer is higher than the first column. The first column provides a drift layer so that a vertical type first-conductive-type channel transistor is formed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.