Stacked chip package and method for forming the same
US7638365B2 · kind B2 · utility
1Cited by
4References
29Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 15, 2007 |
| Grant date | Dec 29, 2009 |
| Priority date | — |
| Expiry date | Jan 9, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Provided is a stacked chip package and a method for forming the same. A spacer is formed on a side of an upper chip. A conductive line is formed on the spacer to electrically connect upper and lower chips. The reliability of the stacked chip package is improved because wire bonding is not used to electrically connect the upper and lower chips. Further, the overall size of the stacked chip package can be reduced as the height of bonding wire loops does not contribute to the overall stacked chip package height.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.