Patent · US Active

Method for producing multi-gate field-effect transistor with fin structure having drain-extended MOS field-effect transistor

US7638370B2 · kind B2 · utility

21Cited by

4References

16Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Harald Gossner · Riemerling, DE
Thomas Schulz · Austin, US
Christian Russ · Diedorf, DE
Gerhard Knoblinger · Villach, AT

Key dates

Filing date	May 8, 2007
Grant date	Dec 29, 2009
Priority date	—
Expiry date	May 8, 2027

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/0002
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

In a method for producing an electronic component, a first doped connection region and a second doped connection region are formed on or above a substrate; a body region is formed between the first doped connection region and the second doped connection region; at least two gate regions separate from one another are formed on or above the body region; at least one partial region of the body region is doped by means of introducing dopant atoms, wherein the dopant atoms are introduced into the at least one partial region of the body region through at least one intermediate region formed between the at least two separate gate regions.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.