Delay locked loop and semiconductor memory device with the same
US7639552B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 28, 2007 |
| Grant date | Dec 29, 2009 |
| Priority date | — |
| Expiry date | Jan 6, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/222
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device is capable of controlling a delay locked loop appropriately based on operation modes, particularly in a fast power-down mode to reduce an amount of current maximally. The semiconductor memory device includes a delay-locked clock signal generating unit, a mode signal generating unit, and a delay locking control unit. The delay-locked clock signal generating unit performs a delay locking operation on a clock signal, thereby generating a delay-locked clock signal. The mode signal generating unit enables a fast precharge power-down mode signal in a fast precharge power-down mode. The delay locking control unit controls the delay-locked clock signal generating unit to be activated in a predetermined cycle in response to the fast precharge power-down mode signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.