Detection circuit for mixed asynchronous and synchronous memory operation
US7640413B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 20, 2007 |
| Grant date | Dec 29, 2009 |
| Priority date | — |
| Expiry date | Mar 20, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/413
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory access mode detection circuit and method for detecting and initiating memory access modes for a memory device The memory access mode detection circuit receives the memory address signals, the control signals, and the clock signal and generates a first mode detection signal in response to receipt of the memory address signals or a first combination of control signals. An first mode initiation signal is generated a time delay subsequent to the detection signal to initiate the first mode memory access operation. In response to receipt of a second combination of control signals and an active clock signal, the memory access mode detection circuit further generates a second mode detection signal to initiate a second mode memory access operation and to suppress generation of the first mode detection signal, thereby canceling the first mode memory access operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.