Three-dimensional package and method of making the same
US7642132B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 23, 2006 |
| Grant date | Jan 5, 2010 |
| Priority date | — |
| Expiry date | Jun 21, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/00014
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a three-dimensional package and a method of making the same. The method comprises: (a) providing a semiconductor body; (b) forming at least one blind hole in the semiconductor body; (c) forming an isolation layer on the side wall of the blind hole; (d) forming a conductive layer on the isolation layer; (e) patterning the conductive layer; (f) removing a part of the lower surface of the semiconductor body and a part of the isolation layer, so as to expose a part of the conductive layer; (g) forming a solder on the lower end of the conductive layer; (h) stacking a plurality of the semiconductor bodies, and performing a reflow process; and (i) cutting the stacked semiconductor bodies, so as to form a plurality of three-dimensional packages. As such, the lower end of the conductive layer and the solder thereon are “inserted” into the space formed by the conductive layer of the lower semiconductor body, so as to enhance the joining between the conductive layer and the solder, and effectively reduce the overall height of the three-dimensional packages after joining.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.