Packaged semiconductor chip comprising an integrated circuit chip ablated with laser and cut with saw blade from wafer
US7642631B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 13, 2007 |
| Grant date | Jan 5, 2010 |
| Priority date | — |
| Expiry date | Nov 22, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/00014
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A packaged semiconductor chip comprising an integrated circuit chip including a low-k dielectric layer and a chip substrate, wherein an edge of the integrated circuit chip has a first edge portion and a second edge portion. At least part of the first edge portion being across a same level as the low-k dielectric layer, and the first edge portion having been laser ablated to have a series of rounded recesses formed therein. The second edge portion being across a same level as at least part of the chip substrate, and the second edge portion having a different surface texture than that of the first edge portion. The packaged semiconductor chip also comprises a packaging substrate having the integrated circuit chip attached and a plurality of solder bumps electrically connecting between the packaging substrate and the integrated circuit chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.