Address/data multiplexed device
US7643371B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 20, 2007 |
| Grant date | Jan 5, 2010 |
| Priority date | — |
| Expiry date | Jun 26, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1078
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device and a method of controlling the semiconductor device, the semiconductor device including: a memory cell array; a terminal that inputs or outputs storage data stored in the memory cell array, and inputs address data indicating an address in the memory cell array at which the storage data is input or output, the terminal including: a first terminal that inputs a first part of the address data; and a second terminal that inputs a second part of the address data, wherein the second part of the address data is included of the entire remaining portion of the address data not including the first part of the address data; a first internal address line and a second internal address line to which the address data is supplied; and a switch that couples the first part of the address data to one of the first internal address line or the second internal address line in accordance with predetermined switch information, while coupling the second part of the address data to the other one of the first internal address line or the second internal address line, when the address data is input to the terminal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.