Apparatus and method for supporting simultaneous storage of trace and standard cache lines
US7644233B2 · kind B2 · utility
3Cited by
36References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 4, 2006 |
| Grant date | Jan 5, 2010 |
| Priority date | — |
| Expiry date | Sep 8, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/6082
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A single unified level one instruction cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instructions consistent with conventional cache lines. A mechanism is described for indexing into the cache, and selecting the desired line. Control is exercised over which lines are contained within the cache. Provision is made for selection between a trace line and a conventional line when both match during a tag compare step.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.