Method and apparatus for fabricating a high dielectric constant transistor gate using a low energy plasma system
US7645710B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 8, 2007 |
| Grant date | Jan 12, 2010 |
| Priority date | — |
| Expiry date | Dec 29, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/667
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention generally provides methods and apparatuses that are adapted to form a high quality dielectric gate layer on a substrate. Embodiments contemplate a method wherein a metal plasma treatment process is used in lieu of a standard nitridization process to form a high dielectric constant layer on a substrate. Embodiments further contemplate an apparatus adapted to “implant” metal ions of relatively low energy in order to reduce ion bombardment damage to the gate dielectric layer, such as a silicon dioxide layer and to avoid incorporation of the metal atoms into the underlying silicon. In general, the process includes the steps of forming a high-k dielectric and then terminating the surface of the deposited high-k material to form a good interface between the gate electrode and the high-k dielectric material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.