Dual channel heterostructure
US7648853B2 · kind B2 · utility
6Cited by
35References
21Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 11, 2006 |
| Grant date | Jan 19, 2010 |
| Priority date | — |
| Expiry date | Mar 15, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/751
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Dual channel heterostructures comprising strained Si and strained Ge-containing layers are disclosed, along with methods for producing such structures. In preferred embodiments, a strain-relaxed buffer layer is deposited on a carrier substrate, a strained Si layer is deposited over the strain-relaxed buffer layer and a strained Ge-containing layer is deposited over the strained Si layer. The structure can be transferred to a host substrate to produce the strained Si layer over the strained Ge-containing layer. By depositing the Si layer first, the process avoids Ge agglomeration problems.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.