III-nitride device passivation and method
US7649215B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 3, 2004 |
| Grant date | Jan 19, 2010 |
| Priority date | — |
| Expiry date | Jan 31, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/111
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An embodiment of a III-nitride semiconductor device and method for making the same may include a low resistive passivation layer that permits the formation of device contacts without damage to the III-nitride material during high temperature processing. The passivation layer may be used to passivate the entire device. The passivation layer may also be provided in between contacts and active layers of the device to provide a low resistive path for current conduction. The passivation process may be used with any type of device, including FETs, rectifiers, schottky diodes and so forth, to improve breakdown voltage and prevent field crowding effects near contact junctions. The passivation layer may be activated with a low temperature anneal that does not impact the III-nitride device regarding outdiffusion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.