Reconfigurable high performance texture pipeline with advanced filtering

US7649538B1 · kind B1 · utility

Assignee

• NVIDIA Corporation · US

Inventors

• Alexander L. Minkin · Los Altos, US
• Joel J. McCormack · Boulder, US
• Paul S. Heckbert · Wilkinsburg, US
• Michael J. M. Toksvig · Palo Alto, US
• Luke Y. Chang · Mountain View, US
• Karim M. Abdalla · Menlo Park, US
• Bo Hong · Mountain View, US
• John W. Berendsen · Beaconsfield, CA
• Walter E. Donovan · Saratoga, US
• Emmett M. Kilgariff · San Jose, US

Key dates

• Filing date: Nov 3, 2006
• Grant date: Jan 19, 2010
• Expiry date: Apr 17, 2028

Classification

• Technology area (CPC G): Physics
• CPC primary: G09G2360/18
• WIPO field: Audio-visual technology
• WIPO sector: Electrical engineering

Abstract

Circuits, methods, and apparatus that provide texture caches and related circuits that store and retrieve texels in a fast and efficient manner. One such texture circuit provides an increased number of bilerps for each pixel in a group of pixels, particularly when trilinear or aniso filtering is needed. For trilinear filtering, texels in a first and second level of detail are retrieved for a number of pixels during a clock cycle. When aniso filtering is performed, multiple bilerps can be retrieved for each of a number of pixels during one clock cycle.