Micro tag array having way selection bits for reducing data cache access power
US7650465B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 18, 2006 |
| Grant date | Jan 19, 2010 |
| Priority date | — |
| Expiry date | Jan 27, 2027 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Processors and systems having a micro tag array that reduces data cache access power. The processors and systems include a cache that has a plurality of datarams, a processor pipeline register, and a micro tag array. The micro tag array is coupled to the cache and the processor pipeline register. The micro tag array stores base address data bits or base register data bits, offset data bits, a carry bit, and way selection data bits. When a LOAD or a STORE instruction is fetched, at least a portion of the base address and at least a portion of the offset of the instruction are compared to data stored in the micro tag array. If a micro tag array hit occurs, the micro tag array generates a cache dataram enable signal. This signal enables only a single dataram of the cache.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.