Method for modeling and verifying timing exceptions
US7650581B2 · kind B2 · utility
8Cited by
5References
19Claims
0Family size
Assignee
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Key dates
| Filing date | May 15, 2007 |
| Grant date | Jan 19, 2010 |
| Priority date | — |
| Expiry date | Feb 18, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3312
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for timing exception verification in integrated circuit (IC) designs included verification of functional false paths as well as multi-cycle paths (MCPs). A false path or a MCP is modeled to a satisfiability formula and the formula is validated using a Boolean satisfiability solver. Time required for timing exception verification can be significantly reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.