Solaiman Rahim
19Patents
4h-index
27Co-inventors
56Inventor score
Filing activity: May 15, 2007 → Oct 30, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7650581B2 | Method for modeling and verifying timing exceptions | Physics | 8 | Active |
| US8285527B2 | Method and system for equivalence checking | Physics | 5 | Active |
| US8656326B1 | Sequential clock gating using net activity and XOR technique on semiconductor designs including already gated pipeline design | Physics | 4 | Active |
| US8042085B2 | Method for compaction of timing exception paths | Physics | 4 | Active |
| US10621296B1 | Generating SAIF efficiently from hardware platforms | Physics | 2 | Active |
| US8635578B1 | System and method for strengthening of a circuit element to reduce an integrated circuit's power consumption | Physics | 1 | Active |
| US8984469B2 | System and method for strengthening of a circuit element to reduce an integrated circuit's power consumption | Physics | 1 | Active |
| US11651129B2 | Selecting a subset of training data from a data pool for a power prediction model | Physics | 1 | Active |
| US12124780B2 | Power estimation using input vectors and deep recurrent neural networks | Physics | 0 | Active |
| US11842132B1 | Multi-cycle power analysis of integrated circuit designs | Physics | 0 | Active |
| US12093620B1 | Multi-cycle power analysis of integrated circuit designs | Physics | 0 | Active |
| US12001768B1 | Enhanced glitch estimation in vectorless power analysis | Physics | 0 | Active |
| US11200149B2 | Waveform based reconstruction for emulation | Physics | 0 | Active |
| US9405872B2 | System and method for reducing power of a circuit using critical signal analysis | Physics | 0 | Active |
| US12254255B1 | Glitch identification and power analysis using simulation vectors | Physics | 0 | Active |
| US11726899B2 | Waveform based reconstruction for emulation | Physics | 0 | Active |
| US12001317B2 | Waveform based reconstruction for emulation | Physics | 0 | Active |
| US11651131B2 | Glitch source identification and ranking | Physics | 0 | Active |
| US8677295B1 | Sequential clock gating using net activity and xor technique on semiconductor designs including already gated pipeline design | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.