Implementing a user design in a programmable logic device with single event upset mitigation
US7650585B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 27, 2007 |
| Grant date | Jan 19, 2010 |
| Priority date | — |
| Expiry date | Jul 21, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/34
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Various approaches for generating an implementation of an electronic circuit design are disclosed. In one approach, a software portion of the design is compiled into software that is executable by a hard processor disposed on a single semiconductor chip with resources of an programmable logic device (PLD). A first synthesized version of a hardware portion of the design is generated for the PLD. A synthesized memory scrubber having an empty block for an address counter is generated, as well as a triple modular redundant (TMR) address counter. The memory in the first synthesized version of the hardware portion of the design is replaced with the memory scrubber, and a complete set of netlists is generated, including a TMR hardware portion of the design and a single instance of the synthesized memory scrubber. A configuration bitstream is generated from the complete set of netlists and stored for later use.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.