Micro chip-scale-package system
US7652382B2 · kind B2 · utility
0Cited by
13References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 9, 2007 |
| Grant date | Jan 26, 2010 |
| Priority date | — |
| Expiry date | Oct 9, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A micro chip-scale-package system including providing a metal pattern on an adhesion material, attaching an integrated circuit die to the metal pattern, and molding an encapsulant over the integrated circuit die and the metal pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.