Packaged microelectronic devices and methods for packaging microelectronic devices
US7655500B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 8, 2008 |
| Grant date | Feb 2, 2010 |
| Priority date | — |
| Expiry date | Feb 20, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/351
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Packaged microelectronic devices and methods for packaging microelectronic devices are disclosed herein. In one embodiment, a method of packaging a microelectronic device including a microelectronic die having a first side with a plurality of bond-pads and a second side opposite the first side includes forming a recess in a substrate, placing the microelectronic die in the recess formed in the substrate with the second side facing toward the substrate, and covering the first side of the microelectronic die with a dielectric layer after placing the microelectronic die in the recess. The substrate can include a thermal conductive substrate, such as a substrate comprised of copper and/or aluminum. The substrate can have a coefficient of thermal expansion at least approximately equal to the coefficient of thermal expansion of the microelectronic die or a printed circuit board.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.