CMOS device with stressed sidewall spacers

US7655991B1 · kind B1 · utility

Assignee

• XILINX, INC. · US

Inventors

• Deepak Nayak · Kanchinakote, IN
• Yuhao Luo · San Jose, US

Key dates

• Filing date: Sep 8, 2005
• Grant date: Feb 2, 2010
• Expiry date: Jan 4, 2026

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S257/90

Abstract

Sidewall spacers on the gate of a MOS device are formed from stressed material so as to provide strain in the channel region of the MOS device that enhances carrier mobility. In a particular embodiment, the MOS device is in a CMOS cell that includes a second MOS device. The first MOS device has sidewall spacers having a first (e.g., tensile) type of residual mechanical stress, and the second MOS device has sidewall spacers having a second (e.g., compressive) type of residual mechanical stress. Thus, carrier mobility is enhanced in both the PMOS portion and in the NMOS portion of the CMOS cell.