Low threshold voltage semiconductor device with dual threshold voltage control means
US7655994B2 · kind B2 · utility
17Cited by
1References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 26, 2005 |
| Grant date | Feb 2, 2010 |
| Priority date | — |
| Expiry date | Dec 31, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor structure, particularly a pFET, which includes a dielectric material that has a dielectric constant of greater than that of SiO2 and a Ge or Si content of greater than 50% and at least one other means for threshold/flatband voltage tuning by material stack engineering is provided. The other means contemplated in the present invention include, for example, utilizing an insulating interlayer atop the dielectric for charge fixing and/or by forming an engineered channel region. The present invention also relates to a method of fabricating such a CMOS structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.