Methods for reducing data cache access power in a processor using way selection bits
US7657708B2 · kind B2 · utility
7Cited by
66References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 18, 2006 |
| Grant date | Feb 2, 2010 |
| Priority date | — |
| Expiry date | Jan 26, 2027 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods for reducing data cache access power in a processor. In an embodiment, a micro tag array is used to store base address or base register data bits, offset data bits, a carry bit, and way selection data bits associated with cache accesses. When a LOAD or a STORE instruction is fetched, at least a portion of the base address and at least a portion of the offset of the instruction are compared to data stored in the micro tag array. If a micro tag array hit occurs, the micro tag array generates a cache dataram enable signal. This signal activates only the cache dataram that stores the needed data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.