Cache leakage shut-off mechanism
US7657767B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2005 |
| Grant date | Feb 2, 2010 |
| Priority date | — |
| Expiry date | Feb 2, 2027 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment of the present invention, a technique is provided to control leakage of a cache sub-array. Other embodiments are disclosed herein. A sleep and shut-off circuit is connected between a virtual supply terminal and a first physical supply terminal to reduce leakage from the cache sub-array when the cache sub-array is disabled in a shut-off mode. The cache sub-array is connected between the virtual supply terminal and a second physical supply terminal. An active circuit is connected to the sleep and shut-off circuit in parallel to enable the cache sub-array in a normal mode and to disable the cache sub-array in the shut-off mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.