Stacked die semiconductor device having circuit tape
US7659608B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 15, 2006 |
| Grant date | Feb 9, 2010 |
| Priority date | — |
| Expiry date | Feb 15, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A stacked die semiconductor package includes a first integrated circuit chip, a first circuit tape coupled to the first integrated circuit chip, a second integrated circuit chip coupled to the first circuit tape, and at least one component coupled to the first circuit tape. The at least one component may include one or more passive components, one or more active components, or a combination of passive and active components. The stacked die semiconductor package can also include a second circuit tape coupled to the second integrated circuit chip and a third integrated circuit chip coupled to the second circuit tape. The stacked die semiconductor package can also include an encapsulant.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.