Test circuit and method for multilevel cell flash memory
US7661041B2 · kind B2 · utility
0Cited by
7References
12Claims
0Family size
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Key dates
| Filing date | Dec 10, 2007 |
| Grant date | Feb 9, 2010 |
| Priority date | — |
| Expiry date | Dec 10, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A test device and method may be used to detect voltage, current or signals of a digital multilevel memory cell system or to test operation or performance by applying inputted voltages, currents or signals to the memory cell system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.