Trim process for critical dimension control for integrated circuits
US7662718B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 9, 2006 |
| Grant date | Feb 16, 2010 |
| Priority date | — |
| Expiry date | Jan 14, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/32139
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of etching substrates employing a trim process for critical dimension control for integrated circuits are disclosed. In one embodiment, the method of etching includes providing a first hard mask layer over a target layer; providing a second hard mask layer over the first hard mask layer; providing a photoresist layer over the second hard mask layer; forming a pattern in the photoresist layer; transferring the pattern into the second hard mask layer; and trimming the second hard mask layer with the photoresist layer on top of the second hard mask layer. The top surface of the second hard mask layer is protected by the photoresist and the substrate is protected by the overlying first hard mask layer during the trim etch, which can therefore be aggressive.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.