Hard mask layer stack and a method of patterning

US7662721B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Dirk Manger · Dresden, DE
• Hocine Boubekeur · Dresden, DE
• Martin Verhoeven · Radebeul, DE
• Nicolas Nagel · Yokohama, JP
• Thomas Tatry · Dresden, DE
• Dirk Caspary · Dresden, DE
• Matthias Markert · Haßfurt, DE

Key dates

• Filing date: Mar 15, 2006
• Grant date: Feb 16, 2010
• Expiry date: Apr 22, 2027

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B20/00
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A hard mask layer stack for patterning a layer to be patterned includes a carbon layer disposed on top of the layer to be patterned, a first layer of a material selected from the group of SiO2 and SiON disposed on top of the carbon layer and a silicon layer disposed on top of the first layer. A method of patterning a layer to be patterned includes providing the above described hard mask layer stack on the layer to be patterned and patterning the silicon hard mask layer in accordance with a pattern to be formed in the layer that has to be patterned.