Flash memory array with a top gate line dynamically coupled to a word line

US7663921B2 · kind B2 · utility

Assignee

• Silicon Storage Technology, Inc. · US

Inventors

• Hieu Van Tran · San Jose, US
• Hung Quoc Nguyen · Carrollton, US
• Anh Ly · San Jose, US
• Sheng-Hsiung Hsueh · San Jose, US
• Sang Thanh Nguyen · Union City, US
• Loc B. Hoang · San Jose, US
• Steve Choi · Irvine, US
• Thuan Vu · San Jose, US

Key dates

• Filing date: Nov 7, 2008
• Grant date: Feb 16, 2010
• Expiry date: Nov 7, 2028

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C29/832
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Systems and methods are disclosed including memory cells arranged in sectors. In one exemplary implementation, each memory cell may include a top gate, a source, a top gate line coupling memory cells in a sector, and a word line coupling memory cells together. Moreover, the top gate line may be dynamically coupled to the word line. Other exemplary implementations may relate to drivers for driving the word line and/or top gate line, multilevel memory cell, and/or floating gate line features.