Prioritizing thread selection partly based on stall likelihood providing status information of instruction operand register usage at pipeline stages
US7664936B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 4, 2005 |
| Grant date | Feb 16, 2010 |
| Priority date | — |
| Expiry date | Jan 18, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3861
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus for scheduling dispatch of instructions among a plurality of threads being concurrently executed in a multithreading processor is provided. The apparatus includes an instruction decoder that generate register usage information for an instruction from each of the threads, a priority generator that generates a priority for each instruction based on the register usage information and state information of instructions currently executing in an execution pipeline, and selection logic that dispatches at least one instruction from at least one thread based on the priority of the instructions. The priority indicates the likelihood the instruction will execute in the execution pipeline without stalling. For example, an instruction may have a high priority if it has little or no register dependencies or its data is known to be available; or may have a low priority if it has strong register dependencies or is an uncacheable or synchronized storage space load instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.