Method for forming a dual metal gate structure

US7666730B2 · kind B2 · utility

Assignee

• Freeescale Semiconductor, Inc. · US

Inventors

• Gauri Karve · Cohoes, US
• Cristiano Capasso · Austin, US
• Srikanth B. Samavedam · Austin, US
• James K. Schaeffer · Austin, US
• William J. Taylor, Jr. · Clifton Park, US

Key dates

• Filing date: Jun 29, 2007
• Grant date: Feb 23, 2010
• Expiry date: Jul 30, 2028

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0181

Abstract

A method for forming a semiconductor structure includes forming a channel region layer over a semiconductor layer where the semiconductor layer includes a first and a second well region, forming a protection layer over the channel region layer, forming a first gate dielectric layer over the first well region, forming a first metal gate electrode layer over the first gate dielectric, removing the protection layer, forming a second gate dielectric layer over the channel region layer, forming a second metal gate electrode layer over the second gate dielectric layer, and forming a first gate stack including a portion of each of the first gate dielectric layer and the first metal gate electrode layer over the first well region and forming a second gate stack including a portion of each of the second gate dielectric layer and the second metal gate electrode layer over the channel region layer.