Methods for fabricating a split charge storage node semiconductor memory

US7666739B2 · kind B2 · utility

Assignee

• Spansion LLC. · US

Inventors

• Chungho Lee · Sunnyvale, US
• Ashot Melik-Martirosian · San Diego, US
• Hiroyuki Kinoshita · San Jose, US
• Kuo-Tung Chang · Saratoga, US
• Sugimo Rinji · San Jose, US
• Wei Zheng · Beijing, CN

Key dates

• Filing date: Dec 20, 2006
• Grant date: Feb 23, 2010
• Expiry date: Feb 27, 2028

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/037

Abstract

Methods are provided for fabricating a split charge storage node semiconductor memory device. In accordance with one embodiment the method comprises the steps of forming a gate insulator layer having a first physical thickness and a first effective oxide thickness on a semiconductor substrate and forming a control gate electrode having a first edge and a second edge overlying the gate insulator layer. The gate insulator layer is etched to form first and second undercut regions at the edges of the control gate electrode, the first and second undercut region each exposing a portion of the semiconductor substrate and an underside portion of the control gate electrode. First and second charge storage nodes are formed in the undercut regions, each of the charge storage nodes comprising an oxide-storage material-oxide structure having a physical thickness substantially equal to the first physical thickness and an effective oxide thickness less than the first effective oxide thickness.