Multilevel-cell memory structures employing multi-memory with tungsten oxides and manufacturing method
US7667220B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 19, 2007 |
| Grant date | Feb 23, 2010 |
| Priority date | — |
| Expiry date | Aug 9, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8833
Abstract
The present invention provides multilevel-cell memory structures with multiple memory layer structures where each memory layer structure includes a tungsten oxide region that defines different read current levels for a plurality of logic states. Each memory layer structure can provide two bits of information, which constitutes four logic states, by the use of the tungsten oxide region that provides multilevel-cell function in which the four logic states equate to four different read current levels. A memory structure with two memory layer structures would provide four bits of storage sites and 16 logic states. In one embodiment, each of the first and second memory layer structures includes a tungsten oxide region extending into a principle surface of a tungsten plug member where the outer surface of the tungsten plug is surrounded by a barrier member.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.