Patent · US Active

Integrated circuit arrangement having a plurality of conductive structure levels and capacitor, and a method for producing the integrated circuit arrangement

US7667256B2 · kind B2 · utility

6Cited by

8References

17Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Martina Hommel · Munich, DE
Heinrich Koerner · Bruckmühl, DE
Markus Schwerd · Holzkirchen, DE
Martin Seck · Birkenfeld, DE

Key dates

Filing date	Sep 21, 2006
Grant date	Feb 23, 2010
Priority date	—
Expiry date	Oct 4, 2027

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/0002
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

An integrated circuit arrangement is disclosed. In one embodiment, the integrated circuit arrangement includes at least three conductive structure levels in which in each case elongated interconnects are arranged.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.