Dynamic random access memory circuit, design structure and method
US7668003B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 24, 2008 |
| Grant date | Feb 23, 2010 |
| Priority date | — |
| Expiry date | Apr 24, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/488
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a DRAM circuit that incorporates an improved reference cell, has half the capacitance of the memory cell, does not require a particular reference voltage, and can be formed using the same fabrication processes as the memory cell. This DRAM circuit comprises a memory cell with a single trench capacitor and a reference cell having two trench capacitors. The two reference cell trench capacitors are connected in series through a merged buried capacitor plate such that they provide half the capacitance of the memory cell trench capacitor. Additionally, the reference cell trench capacitors have essentially the same structure as the memory cell trench capacitor so that they can be formed in conjunction with the memory cell trench capacitor. Also disclosed are a design structure for the above-described memory circuit and a method for forming the above-described memory circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.