Method and apparatus for limiting power dissipation in test
US7669098B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 7, 2006 |
| Grant date | Feb 23, 2010 |
| Priority date | — |
| Expiry date | Apr 17, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318572
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An embodiment provides a system for testing a circuit. During operation, the system scans-in input values into a first set of flip-flops. The outputs of the first set of flip-flops are coupled with the inputs of a circuit under test, the outputs of the circuit are coupled with the inputs of a set of multiplexers, and the outputs of the set of multiplexers are coupled with the inputs of a second set of flip-flops. Next, the system configures the set of multiplexers using a segment-selection circuit, which causes the outputs of the circuit to be coupled with the inputs of the second set of flip-flops. The system then captures the circuit's output values using the second set of flip-flops. Next, the system scans-out the circuit's output values using the second set of flip-flops. Finally, the system determines whether the chip has a fault using the output values.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.