Treatment for reduction of line edge roughness

US7670760B2 · kind B2 · utility

Assignee

• Freeescale Semiconductor, Inc. · US

Inventors

• Jinmiao J. Shen · Austin, US
• Jonathan Cobb · Austin, US
• William D. Darlington · Austin, US
• Brian Fisher
• Mark D. Hall · Austin, US
• Vikas R. Sheth · Austin, US
• Mehul D. Shroff · Austin, US
• James E. Vasek · Austin, US

Key dates

• Filing date: Mar 6, 2006
• Grant date: Mar 2, 2010
• Expiry date: Aug 7, 2027

Classification

• Technology area (CPC G): Physics
• CPC primary: G03F7/168
• WIPO field: Optics
• WIPO sector: Instruments

Abstract

A method for reducing line edge roughness (LER) in a layer of photoresist is provided. In accordance with the method, a layer of photoresist is applied to a substrate. The layer of photoresist is then patterned and annealed in an atmosphere comprising at least one gas selected from the group consisting of hydrogen, nitrogen and fluorine-containing materials. Preferably, the anneal is performed after patterning the photoresist, but either immediately after, or subsequent to, the trim.