Reliability enhancement process
US7670877B2 · kind B2 · utility
1Cited by
27References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 16, 2007 |
| Grant date | Mar 2, 2010 |
| Priority date | — |
| Expiry date | Oct 16, 2027 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P70/50
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A method of packaging a semiconductor component with a printed wiring board is disclosed. The method includes determining a first distance, applying a thin film onto a surface of the semiconductor component such that the thin film is spaced apart from a support of the semiconductor, applying a solder pad onto the printed wiring board, placing the semiconductor component with the thin film onto the printed wiring board, and positioning the thin film adjacent the solder pad.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.