Method of fabricating strain-silicon CMOS

US7670923B1 · kind B1 · utility

Assignee

• XILINX, INC. · US

Inventors

• Deepak Nayak · Kanchinakote, IN
• Yuhao Luo · San Jose, US

Key dates

• Filing date: Aug 28, 2008
• Grant date: Mar 2, 2010
• Expiry date: Sep 2, 2028

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/038

Abstract

Recesses are formed in the drain and source regions of an MOS transistor. The recesses are formed using two anisotropic etch processes and first and second sidewall spacers. The recesses are made up of first and second recesses, and the depths of the first and second recesses are independently controllable. The recesses are filled with a stressed material to induce strain in the channel, thereby improving carrier mobility. The widths and depths of the first and second recesses are selectable to optimize strain in the channel region.