Methods for fabricating MOS devices having epitaxially grown stress-inducing source and drain regions

US7670934B1 · kind B1 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Rohit Pal · Fishkill, US
• Frank Bin Yang · Mahwah, US

Key dates

• Filing date: Jan 26, 2009
• Grant date: Mar 2, 2010
• Expiry date: Jan 26, 2029

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D86/01

Abstract

Methods of fabricating a semiconductor device on and in a semiconductor substrate having a first region and a second region are provided. In accordance with an exemplary embodiment of the invention, a method comprises forming a first gate stack overlying the first region and a second gate stack overlying the second region, etching into the substrate first recesses and second recesses, the first recesses aligned at least to the first gate stack in the first region, and the second recesses aligned at least to the second gate stack in the second region, epitaxially growing a first stress-inducing monocrystalline material in the first and second recesses, removing the first stress-inducing monocrystalline material from the first recesses, and epitaxially growing a second stress-inducing monocrystalline material in the first recesses, wherein the second stress-inducing monocrystalline material has a composition different from the first stress-inducing monocrystalline material.