Semiconductor chip bump connection apparatus and method
US7670939B2 · kind B2 · utility
55Cited by
7References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 12, 2008 |
| Grant date | Mar 2, 2010 |
| Priority date | — |
| Expiry date | May 12, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/10674
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Various semiconductor chip packages and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes coupling a solder bump to a side of a semiconductor chip and bringing the solder bump into contact with a conductor pad coupled to a substrate and positioned in an opening of a solder mask on the substrate. The conductor pad has a first lateral dimension and the opening has a second lateral dimension that is larger than the first lateral dimension. A metallurgical bond is established between the solder bump and the conductor pad.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.