Storing multicore chip test data
US7673208B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 23, 2007 |
| Grant date | Mar 2, 2010 |
| Priority date | — |
| Expiry date | Apr 16, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2242
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated chip architecture is provided which allows for efficiently testing multiple cores included in the integrated chip architecture and storing corresponding diagnosis data which include an indication of the failure-causing test data and the corresponding test analysis data. Embodiments are provided which enable that the test time and the number of required Input/Output test pins is nearly independent from the number of cores included in the multicore chip. The presented embodiments provide a multicore chip architecture which allows for providing input data to the multiple cores in parallel for simultaneously testing the multiple cores, and analyzing the resulting multiple test outputs on chip. As a result of this analysis embodiments may store on chip an indication for those cores that have not successfully passed the test, together with respective diagnosis data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.