Method of fabricating semiconductor device
US7674696B2 · kind B2 · utility
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1References
10Claims
0Family size
Assignee
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Key dates
| Filing date | Dec 21, 2007 |
| Grant date | Mar 9, 2010 |
| Priority date | — |
| Expiry date | Feb 20, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/324
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a gate insulating layer, a conductive layer, and a metal layer are formed over a semiconductor substrate. An ion implantation region is formed in an interface of the conductive layer and the metal layer by performing an ion implantation process. A flash annealing process is performed on the ion-implanted semiconductor substrate. The metal layer, the conductive layer, and the gate insulating layer are patterned.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.