Non-volatile reprogrammable memory
US7675106B2 · kind B2 · utility
6Cited by
8References
19Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | Sep 22, 2006 |
| Grant date | Mar 9, 2010 |
| Priority date | — |
| Expiry date | Jul 19, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6891
Abstract
A non-volatile memory point including a floating gate placed above a semiconductor substrate, the floating gate comprising active portions insulated from the substrate by thin insulating layers, and inactive portions insulated from the substrate by thick insulating layers that do not conduct electrons, the active portions being principally P-type doped, and the inactive portions comprising at least one N-type doped area forming a portion of a PN junction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.